Semiconductor integrated circuit device which executes data transfer between a plurality of devices connected over network, and data transfer method

ABSTRACT

A semiconductor integrated circuit device includes a first semiconductor device and a second semiconductor device, first and second buffer circuits, a data bus, and a control circuit. The semiconductor integrated circuit device executes data transmission/reception between the first and second semiconductor devices. The first and second buffer circuits store data. The data bus transmits the data between the first and second buffer circuits. The first semiconductor device reads out the transfer data into the first buffer circuit. The control circuit transfers the transfer data, which is stored in the first buffer circuit, to the second buffer circuit via the data bus. The control circuit acquires a right of use of the data bus after the first semiconductor device writes the transfer data into the first buffer circuit, and disclaims the right of use of the data bus after the transfer data is transferred to the second buffer circuit.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is based upon and claims the benefit of priority fromprior Japanese Patent Application No. 2005-136150, filed May 9, 2005,the entire contents of which are incorporated herein by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates generally to a semiconductor integratedcircuit device and a data transfer method, and relates to, for instance,a data transfer scheme of data transfer between a plurality of devicesconnected over a network.

2. Description of the Related Art

In recent years, the amount of data handled in computers has beenincreasing with great rapidity. Accordingly, how to increase a datatransfer speed is very important from the standpoint of enhancement inprocessing speed of computers.

In the prior art, Jpn. Pat. Appln. KOKAI Publication No. 2001-209626 andJpn. Pat. Appln. KOKAI Publication No. H10-116244, for instance,disclose various data transfer techniques such as DMA transfer. In theseprior-art data transfer methods, however, the data transfer speed is notsufficient.

BRIEF SUMMARY OF THE INVENTION

A semiconductor integrated circuit device, which includes a firstsemiconductor device and a second semiconductor device and executes datatransmission/reception between the first and second semiconductordevices, according to an aspect of the present invention includes:

first and second buffer circuits which store data;

a data bus which transmits the data between the first and second buffercircuits;

the first semiconductor device which reads out the transfer data intothe first buffer circuit in a case where the first buffer circuitincludes an empty area at a time of transferring the data;

a control circuit which transfers the transfer data, which is stored inthe first buffer circuit, to the second buffer circuit via the data busin a case where the second buffer circuit includes an empty area at thetime of transferring the data, the control circuit acquiring a right ofuse of the data bus after the first semiconductor device writes thetransfer data into the first buffer circuit, and disclaiming the rightof use of the data bus after the transfer data is transferred to thesecond buffer circuit; and

the second semiconductor device which reads out the transfer datatransferred to the second buffer circuit.

A data transfer method for data transfer between a first semiconductordevice and a second semiconductor device, which are connected over adata bus, according to an aspect of the present invention includes:

causing the first semiconductor device, which functions as atransfer-source semiconductor device, to read out transfer data into afirst buffer circuit;

causing a control circuit to confirm completion of the read-out of thetransfer data into the first buffer circuit, and to acquire a right ofuse of the data bus;

causing the control circuit to transfer the transfer data, which isstored in the first buffer circuit, to a second buffer circuit via thedata bus;

causing the control circuit to disclaim the right of use of the data busafter the transfer of the transfer data;

causing the second semiconductor device to read out the transfer datatransferred to the second buffer circuit.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWING

FIG. 1 is a block diagram of a semiconductor integrated circuit deviceaccording to a first embodiment of the present invention;

FIG. 2 is a conceptual view of a request table that is provided in amaster controller according to the first embodiment of the invention;

FIG. 3 is a flow chart of a data transfer method that is executed by thesemiconductor integrated circuit device according to the firstembodiment of the invention;

FIG. 4 is a block diagram of the semiconductor integrated circuit deviceaccording to the first embodiment of the invention;

FIG. 5 is a conceptual view of a request table that is provided in themaster controller according to the first embodiment of the invention;

FIG. 6 is a block diagram of the semiconductor integrated circuit deviceaccording to the first embodiment of the invention;

FIG. 7 is a block diagram of the semiconductor integrated circuit deviceaccording to the first embodiment of the invention;

FIG. 8 is a timing chart that illustrates a scheme of data transfer bythe semiconductor integrated circuit device according to the firstembodiment of the invention;

FIG. 9 is a timing chart that illustrates a scheme of data transfer andDMA transfer by the semiconductor integrated circuit device according tothe first embodiment of the invention;

FIG. 10 is a timing chart that illustrates a scheme of data transfer bythe semiconductor integrated circuit device according to the firstembodiment of the invention;

FIG. 11 is a block diagram of a semiconductor integrated circuit deviceaccording to a second embodiment of the present invention;

FIG. 12 is a flow chart of a data transfer method that is executed bythe semiconductor integrated circuit device according to the secondembodiment of the invention;

FIG. 13 is a block diagram of the semiconductor integrated circuitdevice according to the second embodiment of the present invention;

FIG. 14 is a block diagram of a master controller that is provided in asemiconductor integrated circuit device according to a third embodimentof the invention;

FIG. 15 is a flow chart of a data transfer method that is executed bythe semiconductor integrated circuit device according to the thirdembodiment of the invention;

FIG. 16 is a block diagram of a master controller, a source data bufferand a destination data buffer that are provided in a semiconductorintegrated circuit device according to a fourth embodiment of theinvention;

FIG. 17 is a conceptual view of a request table that is provided in themaster controller according to the fourth embodiment of the invention;

FIG. 18 is a block diagram of the semiconductor integrated circuitdevice according to the fourth embodiment of the invention;

FIG. 19 is a timing chart that illustrates a scheme of data transfer bythe semiconductor integrated circuit device according to the fourthembodiment of the invention;

FIG. 20 is a block diagram of the semiconductor integrated circuitdevice according to the fourth embodiment of the invention;

FIG. 21 is a block diagram of the semiconductor integrated circuitdevice according to the fourth embodiment of the invention;

FIG. 22 is a conceptual view of a request table that is provided in themaster controller according to the fourth embodiment of the invention;

FIG. 23 is a block diagram of the semiconductor integrated circuitdevice according to the fourth embodiment of the invention;

FIG. 24 is a conceptual view of the request table that is provided inthe master controller according to the fourth embodiment of theinvention;

FIG. 25 is a block diagram of the semiconductor integrated circuitdevice according to the fourth embodiment of the invention;

FIG. 26 is a conceptual view of the request table that is provided inthe master controller according to the fourth embodiment of theinvention;

FIG. 27 is a block diagram of the semiconductor integrated circuitdevice according to the fourth embodiment of the invention;

FIG. 28 is a conceptual view of the request table that is provided inthe master controller according to the fourth embodiment of theinvention;

FIG. 29 is a block diagram of a semiconductor integrated circuit deviceaccording to a fifth embodiment of the invention;

FIG. 30 is a block diagram of a host processor and a master controllerthat are provided in a semiconductor integrated circuit device accordingto a first modification of the first to fifth embodiments of theinvention;

FIG. 31 is a block diagram of a semiconductor integrated circuit deviceaccording to a second modification of the first to fifth embodiments ofthe invention;

FIG. 32 is a block diagram of a semiconductor integrated circuit deviceaccording to a third modification of the first to fifth embodiments ofthe invention; and

FIG. 33 is a block diagram of an image rendering system LSI thatincludes the semiconductor integrated circuit device according to thefirst to fifth embodiments of the invention.

DETAILED DESCRIPTION OF THE INVENTION

A semiconductor integrated circuit device and a data transfer methodaccording to a first embodiment of the present invention will now bedescribed with reference to FIG. 1. FIG. 1 is a block diagram of asemiconductor integrated circuit (LSI) according to this embodiment. Asis shown in FIG. 1, an LSI 1 comprises a master controller (hereinafterabbreviated as “MC”) 10, four semiconductor devices 20-1 to 20-4(hereinafter referred to as “devices A to D”), source data buffers (SDB)30-1 to 30-4, destination data buffers (DDB) 40-1 to 40-4, a buscontroller 50, and a data bus 60.

The devices A to D are independent semiconductor devices, and each ofthe devices A to D includes a CPU, a memory and an input/output circuit.The devices A to D execute mutual data transmission/reception via a databus 60. It should suffice if each of the devices A to D has a datatransfer function, and the structure of devices A to D is not limited tothe above-described one.

The SDBs 30-1 to 30-4 are provided in association with the devices A toD. At a time of data transfer, the SDBs 30-1 to 30-4 temporarily storedata to be transferred, when the devices A to D serve as data transfersources. In the present embodiment, each of the SDBs 30-1 to 30-4 hasonly one entry and can store only data for a single transfer operation.

The DDBs 40-1 to 40-4 are provided in association with the devices A toD. At a time of data transfer, the DDBs 40-1 to 40-4 temporarily storetransferred data, when the devices A to D serve as data transferdestinations. In the present embodiment, each of the DDBs 40-1 to 40-4has only one entry and can store only data for a single transferoperation.

The MC 10 controls data transfer between the devices A to D. The MC 10includes an arbiter 11 and a request table 12. The arbiter 11 instructsthe devices A to D to actually transfer data. The request table 12 isexplained with reference to FIG. 2. FIG. 2 is a conceptual view showingan example of the request table 12.

As is shown in FIG. 2, the request table 12 contains, as information, acurrently outstanding transfer request, a state of the SDB of atransfer-source device associated with the transfer request, and a stateof the DDB of a transfer destination device associated with the transferrequest. In the case of FIG. 2, a transfer request from the device A tothe device B is outstanding. The SDB 30-1 of device A and the DDB 40-2of device B are in an empty state (“0”). In addition, there is atransfer request from the device C to the device D. The SDB 30-3 ofdevice C and the DDB 40-4 of device D store some data and are in anon-empty state (“1”). Further, a transfer request from the device B tothe device C is outstanding, and the SDB 30-2 of device B is in theempty state and the DDB 40-3 of device C is in the non-empty state. Thearbiter 11 refers to the request table and determines which transferrequest is to be executed.

When data transfer between devices is executed, the bus controller 50connects the devices over the bus 60 in response to an instruction fromthe MC 10 so that the devices may become mutually communicable.

Next, referring to FIG. 3, a data transfer method, which is executed bythe LSI 1 according to the present embodiment, is described. FIG. 3 is aflow chart illustrating the data transfer method according to thisembodiment. The data transfer method generally comprises three stages 1to 3. The stage 1 relates to a process in the transfer-source device,the stage 2 relates to a process in the MC 10, and the stage 3 relatesto a process in the transfer destination device. For example, datatransfer from the device A to the device B is described.

To start with, the device A which is the transfer-source device checkswhether the SDB 30-1 is empty or not (step S10). Data transfer isexecuted while a SDB is in an empty state. Thus, if the SDB is notempty, the data transfer stands by until the SDB becomes empty. If theSDB 30-1 is empty, the device A writes data, which is to be transferred,in the SDB 30-1 (step S11). When data write in the SDB 30-1 iscompleted, the device A sends a request instruction REQ and a transferdestination address to the MC 10 (step S12). The request instruction REQis a request signal to the effect that the data in the SDB 30-1 shouldbe transferred to the device B. The transfer destination address is anaddress DstAddr of a memory area in which the transfer data is to bewritten in the destination device B. FIG. 4 illustrates the process insteps S11 and S12. The three steps S10 to S12 are included in the stage1. The device A is required to execute no subsequent process relating tothe data transfer.

Then, the stage 2 begins. The MC 10 updates the request table 12 inresponse to the request instruction REQ (step S20). FIG. 5 shows theupdated request table 12. As is shown in FIG. 5, the request table 12includes the transfer request from the device A to the device B, and theempty/non-empty states of the SDB 30-1 of device A and the DDB 40-2 ofdevice B. Assume now that the DDB 40-2 is empty.

Subsequently, the MC 10 checks whether the DDB 40-2 of thetransfer-destination device B is empty or not (step S21). This isimplemented by reference to the request table 12. In place of step S20,the DDB may be confirmed in this step S21 and the information relatingto the DDB may be written in the request table 12. Data transfer isexecuted while the DDB is in the empty state. Thus, if the DDB 40-2 isin use (step S22), the MC 10 suspends the process until the DDB 40-2becomes empty, and executes a different process if there is anotherrequest (step S23).

If the DDB 40-2 is empty (step S22), data transfer from the device A tothe device B is actually executed. Specifically, the MC 10 instructs thebus controller 50 to connect the device A and device B (step S24).Responding to the request, the bus controller 50 connects the SDB 30-1and the DDB 40-2 so that they become mutually communicable. In otherwords, the devices A and B occupy the bus 60. The MC 10 transfers thedata, which is stored in the SDB 30-1, to the DDB 40-2 over the bus 60(step S25). FIG. 6 illustrates this process.

Upon completion of the data transfer, the bus controller 50 opens thebus 60 in accordance with an instruction from the MC 10. In addition,the MC 10 instructs the transfer-destination device B to take in thedata from the DDB 40-2. In this case, the MC 10 informs thetransfer-destination device B of the destination address DstAddr.Further, the MC 10 updates the request table 12 (step S26).Specifically, the MC 10 deletes the executed transfer request from therequest table 12. These steps S20 to S26 are included in the stage 2.The MC 10 is required to execute no subsequent process relating to thedata transfer.

The process then transits to the stage 3. In the stage 3, as shown inFIG. 7, the transfer-destination device B takes in the data from the DDB40-2 at an arbitrary timing (step S30). The data is written in thememory area corresponding to the destination address DstAddr.

In this manner, the data transfer from the device A to the device B iscompleted. The same method applies to data transfer between otherdevices.

With the LSI according to the above-described embodiment, the followingadvantageous effects (1) to (3) are obtained.

(1) The Data Transfer Efficiency can be Improved (Part 1).

Conventional DMA transfer is generally executed by the following twosteps by a DMA controller. (Step 1) To start with, data is read out oftransfer-source device. Specifically, the DMA controller serves as a busmaster, and acquires the right of use of the bus. The DMA controllerissues a data read-out request to the transfer-source device. Inresponse, the transfer-source device outputs an acknowledge signal,which acknowledges that requested data is to be sent, and the requestdata. Upon receiving the acknowledge signal as a trigger, the DMAcontroller receives the data from the transfer-source device. Then, theDMA controller disclaims the right of use of the bus. (Step 2) Next,data write to a transfer-destination device is executed. Specifically,the DMA controller reacquires the right of use of the bus. The DMAcontroller issues a data write request to the transfer-destinationdevice. If the transfer-destination device completes preparation forreceiving data, it outputs an acknowledge signal. Upon receiving theacknowledge signal as a trigger, the DMA controller outputs the data tothe transfer-destination device. Then, the DMA controller disclaims theright of use of the bus.

In the above-described transfer method, the time period, during whichthe bus is occupied for a single data transfer operation, is a timeperiod from the start to the end of a bus protocol. This time period islonger than the time which is needed for the actual data transfer. Inthe above steps 1 and 2, after the DMA controller acquires the right ofuse of the bus, the bus is continuously occupied until the right of useof the bus is disclaimed. In this case, the bus is occupied not onlyduring a time period when data is actually transferred over the buts,but also the bus is uselessly occupied during a time period fortransmission of necessary signals (“handshake”) between the DMAcontroller and the transfer-source/destination devices for the datatransfer. For example, assume that n-cycles are necessary for a singlebus protocol, and m-cycles correspond to the time during which the busis exactly used for the data transfer. In this case, the bus isuselessly occupied by (n−m) cycles. In particular, if the scale of thesystem is large and many devices execute data transfer over the samebus, the time for signal propagations increases and the time, duringwhich the bus is uselessly occupied for handshake, becomes longer.

In the present embodiment, the SDB and DDB are provided for each of thedevices. The transfer-source device may write transfer data in the SDBat an arbitrary timing, and the transfer-destination device may read outdata from the DDB at an arbitrary timing. In addition, the MC mayexecute data transfer at any time if the DDB is in the empty state.Thus, the MC 10 can reduce the number of items to be determined in orderto execute the data transfer, and the time necessary for handshake canremarkably be made shorter than in the prior art. Accordingly, the timeof useless occupation of the bus by the handshake can be decreased, andthe data transfer speed/efficiency can be enhanced.

Furthermore, in the present embodiment, the MC 10 acquires the right ofuse of the bus only in the stage 2 for the data transfer from the SDB tothe DDB. It is thus possible to prevent the bus from being uselesslyoccupied in the stages 1 and 2.

(2) The Data Transfer Efficiency can be Improved (Part 2).

The data transfer method according to the present embodiment comprisesthe three stages, and the respective stages are executed by thetransfer-source device, MC 10 and transfer-destination device. Thus,these stages can be implemented by a pipeline operation. This point isdescribed referring to FIG. 8.

FIG. 8 is a timing chart illustrating the operation states of the stages1 to 3. For the purpose of simplicity, it is supposed that the timenecessary for each stage is equal, and the transfer-destination DDB isempty when the transfer request is made.

Assume now that data transfer requests have been issued successivelyfrom the devices A to C, as shown in FIG. 8. At time instant t1, thedevice A transfers data to the SDB 30-1 and outputs a requestinstruction REQ for data transfer to the device B (stage 1). At timeinstant t2, the MC 10 acquires the right of use of the bus, andtransfers the data from the SDB 30-1 to the DDB 40-2 of device B (stage2). Then, the MC 10 disclaims the right of use of the bus. At timeinstant t3, after the completion of the data transfer, the device Breads out the transfer data from the DDB 40-2 (stage 3).

On the other hand, at time instant t2, the device C transfers data tothe SDB 30-3 and outputs a request instruction REQ for data transfer tothe device D (stage 1). At time instant t3, the right of use of the bus,which is based on the transfer request by the device A, is alreadydisclaimed. Thus, at time instant t3, the MC 10 reacquires the right ofuse of the bus, and transfers the data from the SDB 30-3 to the DDB 40-4of device D (stage 2). Then, the MC 10 disclaims the right of use of thebus. At time instant t4, after the completion of the data transfer, thedevice D reads out the transfer data from the DDB 40-4 (stage 3). Inshort, the process of the stage 2, which is based on the transferrequest by the device A, overlaps in time with the process of the stage1, which is based on the transfer request by the device C.

Further, at time instant t3, the device B transfers data to the SDB 30-2and outputs a request instruction REQ for data transfer to the device C(stage 1). At time instant t4, the right of use of the bus, which isbased on the transfer request by the device C, is already disclaimed.Thus, at time instant t4, the MC 10 reacquires the right of use of thebus, and transfers the data from the SDB 30-2 to the DDB 40-3 of deviceC (stage 2). Then, the MC 10 disclaims the right of use of the bus. Attime instant t5, after the completion of the data transfer, the device Creads out the transfer data from the DDB 40-3 (stage 3). In short, theprocess of the stage 3, which is based on the transfer request by thedevice A, overlaps in time with the process of the stage 2, which isbased on the transfer request by the device C, and with the process ofthe stage 1, which is based on the transfer request by the device B.

Subsequently, at time instant t4, the device D transfers data to the SDB30-4 and outputs a request instruction REQ for data transfer to thedevice A (stage 1). At time instant t5, the right of use of the bus,which is based on the transfer request by the device B, is alreadydisclaimed. Thus, at time instant t5, the MC 10 reacquires the right ofuse of the bus, and transfers the data from the SDB 30-4 to the DDB 40-1of device A (stage 2). Then, the MC 10 disclaims the right of use of thebus. At time instant t6, after the completion of the data transfer, thedevice A reads out the transfer data from the DDB 40-1 (stage 3). Inshort, the process of the stage 3, which is based on the transferrequest by the device C, overlaps in time with the process of the stage2, which is based on the transfer request by the device B, and with theprocess of the stage 1, which is based on the transfer request by thedevice D. Moreover, the process of the stage 3, which is based on thetransfer request by the device B, overlaps in time with the process ofthe stage 2, which is based on the transfer request by the device D.

As has been described above, the processes in the respective stages canbe executed in a pipeline fashion. As a result, the data transferefficiency can be enhanced. This point is explained with reference toFIG. 9. FIG. 9 is a timing chart illustrating the state of processing inthe stages 1 to 3 of the data transfer method according to the presentembodiment, and the state of processing in the conventional DMAtransfer. In FIG. 9, for the purpose of simplicity, it is assumed thatthe same time period (Δt1) is needed for data transfer in the presentembodiment and the conventional DMA transfer. Actually, needless to say,as has been described in connection with the advantageous effect (1),the time needed for handshake can be decreased in the presentembodiment, and thus the data transfer time can be made shorter than inthe conventional DMA transfer.

As is shown in FIG. 9, in the conventional DMA transfer, the DMACtemporarily retains transfer data, and the bus is continuously occupiedfrom the start to the end of the bus protocol. Consequently, it isdifficult to execute a plurality of transfer processes in a parallelfashion. As shown in FIG. 9, a total time of (4×Δt1) is needed.

By contrast, in the transfer method of this embodiment, the MC 10 doesnot retain transfer data, and executes direct data transfer between theSDB and DDB. The four transfer processes of device A→device B, deviceC→device D, device B→device C, and device D→device A are partlyoverlapped so that the stages 2 of the respective processes maysuccessively be performed. Thus, the time needed to complete alltransfer processes is (2×Δt1), which is half the time in the prior art.

(3) The Data Transfer Efficiency can be Improved (Part 3).

In the data transfer method according to the present embodiment, thestage 1 is executed for the device whose SDB is empty. The stage 1 isthe process executed in each of the devices, regardless of the state ofother devices. It is thus possible that a plurality of devices transferdata to the associated SDBs and output request instructions REQ to theMC 10 in the same time zone. If the MC 10 receives a plurality ofrequest instructions, the MC 10 preferentially executes a requestinstruction associated with an empty-state DDB of thetransfer-destination device. In short, the data transfer is executed inan “out-of-order” fashion. Therefore, the data transfer efficiency canbe improved.

This process is described with reference to FIG. 10. FIG. 10 is a timingchart illustrating the states of operations of the stages 1 to 3 and thestates of the SDBs and DDBs of the devices. Assume now that the devicesA to D have determined data transfer at time instants t1 to t4, as inthe case of FIG. 9.

To start with, at time instant t1, the device A determines data transferto the device B. At time instant t1, however, the SDB 30-1 is in use, sothe device A postpones the data transfer.

At time instant t2, the device C determines data transfer to the deviceD. At time instant t2, the SDB 30-3 is empty, so the device C transfersdata to the SDB 30-3 and outputs a request instruction REQ1 to the MC10. In addition, since the SDB 30-1 has become empty at time instant t2,the device A transfers data to the SDB 30-1 and outputs a requestinstruction REQ2 to the MC 10.

At time instant t3, the device B determines data transfer to the deviceC. At time instant t3, however, the SDB 30-2 is in use, so the device Bpostpones the data transfer. In addition, since the DDB 40-2 is in useand the DDB 40-4 is empty, the MC 10 keeps the request instruction REQ2outstanding, and executes the data transfer relating to the requestinstruction REQ1. Specifically, the MC 10 transfers the data from theSDB 30-3 to the DDB 40-4.

At time instant t4, the device D determines data transfer to the deviceA. At time instant t4, however, the SDB 30-4 is in use, so the device Dpostpones the data transfer. In addition, since the SDB 30-2 is still inuse, the device B further postpones the data transfer. Besides, sincethe DDB 40-2 is still in use, the MC 10 further keeps the requestinstruction REQ2 outstanding.

At time instant t5, the SDB 30-2 becomes empty, so the device Btransfers data to the SDB 30-2 and outputs a request instruction REQ3 tothe MC 10. Since the DDB 40-2 is still in use, the MC 10 further keepsthe request instruction REQ2 outstanding.

At time instant t6, the SDB 30-4 becomes empty, so the device Dtransfers data to the SDB 30-4 and outputs a request instruction REQ4 tothe MC 10. Although the DDB 40-2 is still in use, the DDB 40-3 is nowempty. Thus, the MC 10 executes the request instruction REQ3, prior tothe request instruction REQ2.

At time instant t7, the DDB 40-2 becomes empty, so the MC 10 executesthe request instruction REQ2. At time instant t8, the MC 10 executes therequest instruction REQ4.

As has been described above, the MC 10 executes request instructions,not in the order of reception of request instructions, but in the orderbeginning with a request instruction associated with executable datatransfer. Thus, unless waiting period is not required and the datatransfer efficiency can be improved.

(4) The Processing Efficiency of Each Device can be Improved.

In the data transfer method according to the present embodiment, the SDBand DDB are provided for each device. Thus, once the transfer-sourcedevice has written data in the associated SDB, it completes the processfor data transfer and transfer-destination device is not required toexecute any further process until the data is read out of the DDB. Inother words, the transfer-source device is released from the datatransfer process in the stages 2 and 3, and can execute its ownindependent process. Moreover, in the stages 1 and 2, thetransfer-destination device is not required to execute the data transferprocess and can execute its own independent process during the timeperiod of stages 1 and 2. Therefore, it is possible to prevent thedevices from being unnecessarily occupied by the data transfer process,and the processing efficiency of each device can be enhanced.

Next, a semiconductor integrated circuit device and a data transfermethod according to a second embodiment of the present invention aredescribed with reference to FIG. 11. FIG. 11 is a block diagram of anLSI according to this embodiment. The present embodiment relates to acase in which the MC 10 receives a request instruction from a blockother than the devices A to D.

As is shown in FIG. 11, the LSI 1 of this embodiment further comprises ahost processor 70 in addition to the structure shown in FIG. 1, whichhas been described in connection with the first embodiment. The hostprocessor 70 issues a request for data transfer between devices A to Dto the MC 10, and outputs a request instruction to the MC 10.

A data transfer method executed by the LSI 1 of this embodiment isdescribed with reference to FIG. 12. FIG. 12 is a flow chartillustrating the data transfer method according to this embodiment.

To start with, the process in the stage 1 is executed. The hostprocessor 70 outputs a request instruction, REQ1 to REQn (n: naturalnumber), to the MC 10 (step S40). FIG. 13 illustrates this state. As isshown in FIG. 13, the host processor 70 sends a transfer-source addressSrcAddr and a transfer-destination address DstAddr, as well as therequest instruction, to the MC 10. The transfer-source address SrcAddris an address of an area in the transfer-source device, where data to betransferred is stored.

Upon receiving the request instruction, REQ1 to REQn, the MC 10 updatesthe request table 12 (step S41). That is, the request table 12 storesthe request content, and the empty/non-empty states of the associatedSDB and DDB. The MC 10 checks whether the SDB of the transfer-sourcedevice is empty (step S42). This is implemented by reference to therequest table 12. In place of step S41, the SDB and DDB may be confirmedin this step S42 and the information relating to the SDB and DDB may bewritten in the request table 12. Data transfer is executed with respectto the device, the SDB of which is in the empty state. Thus, if the SDBis in use (step S43), the MC 10 keeps the associated request instructionoutstanding until the SDB becomes empty, and executes a differentprocess if there is another request (step S44).

If the SDB of the transfer-source device is empty (step S43), the MC 10instructs any one of the devices A to D to read out data into the SDB(step S45). This instruction is referred to as “read-out instruction”.The read-out instruction includes the transfer-source address SrcAddr.If request instructions are given and there are a plurality of deviceswhose SDBs are empty, the arbiter 11 selects the device, for which therequest instruction is to be preferentially executed, and thus theprocess in step S45 is executed.

The device which has received the data read-out instruction reads outdata, which is stored at the transfer-source address SrcAddr, into theSDB (step S46). If the data write in the SDB is completed, thetransfer-source device outputs an acknowledge signal to the MC 10 (stepS47).

The process in the stage 1 is thus completed, and the MC 10 that hasreceived the acknowledge signal advances to the process of the stage 2.In this embodiment, since the request table 12 is updated in step S41,it is not necessary to execute the process of step S20. Thus, the stage2 begins with the process of step S21. The subsequent process is thesame as has been described in connection with the first embodiment. Inthe present embodiment, too, the stages 1 to 3 are processed in thepipeline fashion.

As has been described above, according to the present embodiment, evenin the case where the transfer instruction is received from a blockother than devices that execute mutual data transmission/reception, theadvantageous effects (1) to (4) that have been described in connectionwith the first embodiment can be obtained.

Next, a semiconductor integrated circuit device and a data transfermethod according to a third embodiment of the present invention aredescribed. In the third embodiment, the transfer-source device, in placeof the MC 10 in the second embodiment, checks the empty/non-empty stateof the SDB.

FIG. 14 is a block diagram of the device A included in the LSI 1according to the third embodiment. As is shown in FIG. 14, the device Aincludes a memory 21 having a plurality of entries. The memory 21 storestransfer-source addresses SrcAddr, which are sent from the MC 10, at therespective entries. Similarly, the devices B to D include memories 21.In the other respects, the structure of the third embodiment is the sameas that of the second embodiment as shown in FIG. 11, so a descriptionis omitted here.

A data transfer method executed by the LSI 1 of this embodiment isdescribed with reference to a flow chart of FIG. 15. Following the stepsS40 and S41 that have been described in connection with the secondembodiment, the MC 10 outputs read-out instructions on the basis of arequest instruction REQ, thus instructing the transfer-source device toread out data into the SDB (step S50). The read-out instructions aresuccessively output, without consideration to the data transfer state ofthe transfer-source device, that is, the empty/non-empty state of theSDB.

The transfer-source device, which has received the read-out instruction,stores the read-out instruction (source address SrcAddr) in the memory21 (step S51). Specifically, the transfer-source device can store anumber of read-out instructions, which corresponds to the number ofentries in the memory 21. Subsequently, the transfer-source deviceconfirms the empty/non-empty state of the SDB (step S52).

If the SDB is empty (step S43), the transfer-source device reads out thedata, which is designated by the read-out instruction, into the SDB(step S53). In this case, the data read-out to the SDB may be executedin the order of reception of read-out instructions, or in an alteredorder. For example, when the MC 10 outputs the read-out instruction tothe transfer-source device, the MC 10 may also send information aboutthe state of the DDB of a transfer-destination device, and thetransfer-source device may preferentially read out data relating to therequest instruction associated with the empty DDB, on the basis of theinformation about the state of the DDB.

After the transfer-source device reads out the data into the SDB (stepS46), it returns an acknowledge signal to the MC 10 (step S47). In thiscase, the transfer-source device sends, for instance, thetransfer-source address SrcAddr, along with the acknowledge signal, tothe MC 10. Thereby, the MC 10 can understand with respect to whichrequest instruction the transfer-source device has completed the dataread-out.

Subsequently, the process beginning with the stage 2 (step S21), whichhas been described in connection with the second embodiment, isexecuted.

With the data transfer method according to the above-described thirdembodiment, the same advantageous effects (1) to (4) as with the firstand second embodiments are obtained. Additionally, the followingadvantageous effects (5) and (6) can be obtained.

(5) The Load on the MC 10 can be Reduced.

According to the structure of this embodiment, each device includes thememory 21 having a plurality of entries. Transfer-source addressesSrcAddr, which are sent from the MC 10, are stored at the entries. Sinceeach device can store the plural transfer-source addresses SrcAddr, theMC 10 does not need to confirm the empty/non-empty state of the SDB ofthe transfer-source device, and the load of processing on the MC 10 canbe reduced.

(6) The Data Transfer Efficiency can be Improved (Part 4).

As stated in connection with the above advantageous effect (5), eachdevice stores a plurality of transfer-source addresses SrcAddr. Thus,the transfer-source device can execute data read-out with respect to anarbitrary one of the plurality of transfer-source addresses SrcAddr,which are stored in itself. In other words, the transfer-source devicecan execute data transfer to the SDB in an out-of-order fashion. Thus,the data transfer efficiency can be improved. This point will further bedescribed below.

First, as described above, the data transfer can be executed withrespect to the request instruction that is associated with the emptyDDB. Therefore, the transfer efficiency can be improved.

Second, in the device associated with the data transfer, there is apredetermined delay time from reception of a transfer instruction fromthe MC 10 to data write in the SDB, or to data read-out from the DDB.There is a case in which this delay time varies from address to addresseven within the same device. Thus, the transfer-source device confirmsthe transfer-source addresses SrcAddr stored in the memory 21, andtransfers the data, which can be read out earliest. Thereby, thetransfer efficiency can be enhanced.

Next, a semiconductor integrated circuit device and a data transfermethod according to a fourth embodiment of the present invention aredescribed. In the fourth embodiment, each of the SDB and DDB in thethird embodiment includes a plurality of entries.

FIG. 16 is a block diagram showing a device A, an SDB 30-1 and a DDB40-1, which are included in the LSI 1 according to the fourthembodiment. As is shown in FIG. 16, the device A includes the memory 21which has been described in connection with the third embodiment. TheSDB 30-1 includes (m+1) entries (m: a natural number of 1 or more), andthe DDB 40-1 includes (k+1) entries (k: a natural number of 1 or more).Similarly, each of the devices B to D includes the memory 21, and eachof the SDBs 30-2 to 30-4 and each of the DDBs 40-2 to 40-4 includes aplurality of entries. Thus, each of the SDBs 30-1 to 30-4 and each ofthe DDBs 40-1 to 40-4 can store a plurality of transfer data. FIG. 17 isa conceptual view of a request table 12 included in the MC 10 accordingto this embodiment. As is shown in FIG. 17, the request table 12according to the present embodiment stores the contents of requestinstructions, transfer-source addresses and transfer-destinationaddresses, which correspond to the respective entries in the SDB andDDB, in association with the devices A to D. In the other respects, thestructure of the fourth embodiment is the same as that of the thirdembodiment.

Next, a data transfer method executed by the LSI 1 according to thepresent embodiment is described. The process of data transfer accordingto this embodiment is substantially the same as illustrated in the flowchart of FIG. 15 in connection with the third embodiment. The datatransfer process of the fourth embodiment differs from that of the thirdembodiment in that the SDB and DDB store a plurality of transfer data.For simple description, assume now that the LSI 1 comprises threedevices A to C, and that the number of entries in the memory 21, each ofthe SDBs 30-1 to 30-3 and each of the DDBs 40-1 to 40-3 is four, asshown in FIG. 18. In addition, assume that the data transfer is executedin an order as illustrated in FIG. 19. FIG. 19 is a timing chart showingthe processes in stages 1 and 2.

To start with, as shown in FIG. 18, the host processor 70 delivers sixrequest instructions REQ1 to REQ6 to the MC 10 (step S40). The contentsof request instructions REQ1 to REQ6 are as follows:

*REQ1: To transfer data 1, which is stored in device A, to device B;

Address in device A where data 1 is stored=SrcAddr1,

Address in device B where data 1 is to be stored=DstAddr1,

*REQ2: To transfer data 2, which is stored in device A, to device B;

Address in device A where data 2 is stored=SrcAddr2,

Address in device B where data 2 is to be stored DstAddr2,

*REQ3: To transfer data 3, which is stored in device A, to device B;

Address in device A where data 3 is stored=SrcAddr3,

Address in device B where data 3 is to be stored=DstAddr3,

*REQ4: To transfer data 4, which is stored in device A, to device C;

Address in device A where data 4 is stored=SrcAddr4,

Address in device C where data 4 is to be stored=DstAddr4,

*REQ5: To transfer data 5, which is stored in device B, to device A;

Address in device B where data 5 is stored=SrcAddr5,

Address in device A where data 5 is to be stored=DstAddr5,

*REQ6: To transfer data 6, which is stored in device C, to device A;

Address in device C where data 6 is stored=SrcAddr6,

Address in device A where data 6 is to be stored=DstAddr6.

As is shown in FIG. 20, the MC 10, which has received the requestinstructions REQ1 to REQ6, forwards read-out instructions based on therequest instructions REQ1 to REQ4 to the device A, forwards a read-outinstruction based on the request instruction REQ5 to the device B, andforwards a read-out instruction based on the request instruction REQ6 tothe device C (step S50).

The devices A to C, which have received the read-out instructions, storetransfer-source addresses in their memories 21 (step S51). Specifically,the entries 0 to 3 in the memory 21 of device A store addresses SrcAddr1to SrcAddr4, the entry 0 in the memory 21 of device B stores an addressSrcAddr5, and the entry 0 in the memory 21 of device C stores an addressSrcAddr6.

Subsequently, the devices A to C check the empty/non-empty states of theSDBs 30-1 to 30-3 and transfer data to empty entries. Assume now thatall entries in the SDBs 30-1 to 30-3 are empty. The device A reads outdata 2, which can be read out earliest, from the address SrcAddr2, andwrites the read-out data 2 in the entry 0 of the SDB 30-1 (step S52,S43, S44, time instant t1 in FIG. 19). The device B reads out data 5from the address SrcAddr5, and writes the read-out data 5 in the entry 0of the SDB 30-2. The device C reads out data 6 from the addressSrcAddr6, and writes the read-out data 6 in the entry 0 of the SDB 30-3.FIG. 21 illustrates this process.

When the data write in the SDBs 30-1 to 30-3 is completed, the devices Ato C return acknowledge signals to the MC 10 (step S47). Responding tothe acknowledge signals, the MC 10 updates the request table 12. FIG. 22shows the updated request table 12. As is shown in FIG. 22, the entry 0of the SDB of device A, the entry 0 of the SDB of device B and the entry0 of the SDB of device C store information corresponding to the requestinstructions REQ2, REQ5 and REQ6. It is supposed that all entries of theDDB 40-2 of device B are in use.

At time instant t2, the MC 10 starts the process of stage 2. The arbiter11 determines which of the request instructions REQ2, REQ5 and REQ6 isto be executed. For this purpose, the arbiter 11 checks the requesttable 12 and confirms the empty/non-empty states of the DDBs (step S21).It is understood from the request table 12 that the DDB 40-1 of device Aand the DDB 40-3 of device C are empty and the DDB 40-2 of device B isall in use (step S43). Since the request instructions REQ5 and REQ6 areexecutable, the arbiter 11 executes, for instance, the requestinstruction REQ5. Specifically, as shown in FIG. 23, the arbiter 11instructs the bus controller 50 to connect the devices A and B (stepS24). The data 5 within the entry 0 of the SDB 30-2 of device B istransferred to the entry 0 of the DDB 40-1 of device A (step S25). Uponcompletion of the data transfer, the MC 10 opens the bus 60 andinstructs the device A to write the data 5, which is stored in the DDB40-1, into the address DstAddr5 (step S26).

In addition, at time instant t2, as shown in FIG. 23, the device Acontinues the process of stage 1. The read-out instructions based on therequest instructions REQ1, REQ3 and REQ4 are still outstanding in thedevice A. After the device A checks the empty/non-empty states of theSDB 30-1 (step S52), the device A reads out the data 1, which is basedon the request instruction REQ1, from the address SrcAddr1 and writesthe data 1 in the entry 1 of the SDB 30-1 (step S43, S44). The device Athen returns an acknowledge signal to the MC 10 (step S47).

When the transfer of the data 5 (step S25) is completed and theacknowledge signal from the device A is received, the MC 10 updates therequest table 12 (step S26). FIG. 24 shows the updated request table. Asis shown in FIG. 24, the information corresponding to the requestinstruction REQ1 is stored in the entry 1 of the SDB of device A. Sincethe data 5 has been transferred from the device B to the device A, theinformation corresponding to the request instruction REQ5 is deletedfrom the device B and is rewritten in the entry 0 of the device A.

At time instant t3, the arbiter 11 determines which of the requestinstructions REQ1, REQ2 and REQ6 is to be executed. Since the DDB ofdevice B is still all in use (step S21, S22), the arbiter 11 executesthe request instruction REQ6. Specifically, as shown in FIG. 25, thearbiter 11 instructs the bus controller 50 to connect the device A anddevice C (step S24). The data 6 in the entry 0 of the SDB 30-3 of deviceC is transferred to the entry 1 of the DDB 40-1 of device A (step S25).Upon completion of the transfer, the MC 10 opens the bus 60 andinstructs the device A to write the data 6, which is stored in the DDB40-1, into the address DstAddr6 (step S26).

In addition, at time instant t3, as shown in FIG. 25, the device Acontinues the process of stage 1. The read-out instructions based on therequest instructions REQ3 and REQ4 are still outstanding in the deviceA. After the device A checks the empty/non-empty states of the SDB 30-1(step S52), the device A reads out the data 4, which is based on therequest instruction REQ4, from the address SrcAddr4 and writes the data4 in the entry 2 of the SDB 30-1 (step S43, S44). The device A thenreturns an acknowledge signal to the MC 10 (step S47).

If the transfer of the data 6 (step S25) is completed and theacknowledge signal from the device A is received, the MC 10 updates therequest table 12 (step S26). FIG. 26 shows the updated request table. Asis shown in FIG. 26, the information corresponding to the requestinstruction REQ4 is stored in the entry 2 of the SDB of device A. Sincethe data 6 has been transferred from the device C to the device A, theinformation corresponding to the request instruction REQ6 is deletedfrom the device C and is rewritten in the entry 1 of the device A.

At time instant t4, the arbiter 11 determines which of the requestinstructions REQ1, REQ2 and REQ4 is to be executed. Since the DDB ofdevice B is still all in use (step S21, S22), the arbiter 11 executesthe request instruction REQ4. Specifically, as shown in FIG. 27, thearbiter 11 instructs the bus controller 50 to connect the device A anddevice C (step S24). The data 4 in the entry 2 of the SDB 30-1 of deviceA is transferred to the entry 0 of the DDB 40-3 of device C (step S25).Upon completion of the transfer, the MC 10 opens the bus 60 andinstructs the device C to write the data 4, which is stored in the DDB40-3, into the address DstAddr4 (step S26).

In addition, at time instant t4, as shown in FIG. 27, the device Acontinues the process of stage 1. Specifically, the device A reads outthe data 3, which is based on the request instruction REQ3, from theaddress SrcAddr3 and writes the data 3 in the entry 3 of the SDB 30-1(step S52, S43, S44, S46). The device A then returns an acknowledgesignal to the MC 10 (step S47).

If the transfer of the data 4 (step S25) is completed and theacknowledge signal from the device A is received, the MC 10 updates therequest table 12 (step S26). FIG. 28 shows the updated request table. Asis shown in FIG. 28, the information corresponding to the requestinstruction REQ3 is stored in the entry 3 of the SDB of device A. Sincethe data 4 has been transferred from the device A to the device C, theinformation corresponding to the request instruction REQ4 is deletedfrom the device A and is rewritten in the entry 0 of the DDB of thedevice C. Assume that at this time instant all the entries in the DDB40-2 of device B have become empty.

At time instant t5, the arbiter 11 determines which of the requestinstructions REQ1, REQ2 and REQ3 is to be executed. Since the DDB ofdevice B is empty (step S21, S22), the arbiter 11 executes the requestinstruction REQ2, with respect to which data write to the device B isexecutable earliest. Specifically, the arbiter 11 instructs the buscontroller 50 to connect the device A and device B, and transfers thedata 2 in the entry 0 of the SDB 30-1 of device A to the entry 0 of theDDB 40-2 of device B (step S24, S25). Thereafter, the MC 10 opens thebus 60 and instructs the device B to write the data 2, which is storedin the DDB 40-2, into the address DstAddr2 (step S26). Further, the MC10 updates the request table (step S26).

Subsequently, at time instants t6 and t7, the arbiter 11 executes therequest instructions REQ1 and REQ3 in the same manner, and transfers thedata 1 and data 3 from the device A to the device B.

Through the above-described process, the execution of the requestinstructions REQ1 to REQ7 by the host processor 70 is completed.Although a description of data write from the DDBs to the devices isomitted, this data write process may be executed by each device at anarbitrary timing. If a plurality of data are present in the DDB, thedata write may be executed in an order of addresses beginning with onefor which the data write is executable earliest.

With the LSI according to the above-described fourth embodiment of theinvention, the following advantageous effect (7) can be obtained inaddition to the advantageous effects (1) to (6).

(7) The Data Transfer Efficiency can be Improved (Part 5).

According to the structure of the fourth embodiment, each of the SDB andDDB includes a plurality of entries and thus can store a plurality oftransfer data. The MC 10 can optimally alter the order of transfer ofdata read out into the SDB by the transfer-source device. In addition,the transfer-destination device can take in the plural data, which arestored in the DDB, in the optimal order. The data transfer in theout-of-order fashion can be implemented, and the standby time for theexecution of transfer can be reduced. Therefore, the transfer efficiencycan be enhanced.

Next, a semiconductor integrated circuit device and a data transfermethod according to a fifth embodiment of the present invention aredescribed. In the fifth embodiment, the bus 60 in each of the first tofourth embodiment is configured to have an interconnection-type networkarchitecture. FIG. 29 is a block diagram of an LSI 1 according to thefifth embodiment. The fifth embodiment is common to the first to fourthembodiments except for the bus architecture, so a description of commonparts is omitted.

As is shown in FIG. 29, the bus 60 has an interconnection-type networkarchitecture. The interconnection-type network is a set of transmissionlines associated with all combinations of devices A to D. The bus 60comprises multiplexers 61-1 to 61-4 and data transmission lines 62-1 to62-4. The transmission line 62-1 transmits an output from the SDB 30-1to the inputs of the multiplexers 61-1 to 61-4. The transmission line62-2 transmits an output from the SDB 30-2 to the inputs of themultiplexers 61-1 to 61-4. The transmission line 62-3 transmits anoutput from the SDB 30-3 to the inputs of the multiplexers 61-1 to 61-4.The transmission line 62-4 transmits an output from the SDB 30-4 to theinputs of the multiplexers 61-1 to 61-4. The transmission lines 62-1 to62-4 transfer data independently. The multiplexer, 61-1 to 61-4, selectsany one of the transmission lines 62-1 to 62-4, and outputs data, whichis sent through the selected transmission line, to the associated DDB,40-1 to 40-4. The arbiter 11 of the MC 10 executes a control as to whichof the transmission lines 62-1 to 62-4 is to be selected by themultiplexer, 61-1 to 61-4.

In the above-described structure, if the number of devices that areconnected is n, an n-number of data can be transferred via theinterconnection-type network. In this case, the structure that includesa given transfer-source device, a given transfer-destination device anda transmission line that connects these devices is equivalent to thestructure as described in the first to fourth embodiments. Thus, theabove-described embodiments can be implemented with the application ofthe interconnection-type network.

With the structure according to the present embodiment, the followingadvantageous effect (8) can be obtained in addition to the advantageouseffects (1) to (7).

(8) The Data Transfer Efficiency can be Improved (Part 6).

According to the present embodiment, with use of theinterconnection-type network, the same number of data as thetransmission lines 62-1 to 62-4 can be transferred in parallel. Thus,the data transfer efficiency can be improved. FIG. 29 exemplifies thecase in which the multiplexers 61-1 to 61-4 are controlled by the MC lb.Alternatively, the multiplexers 61-1 to 61-4 may be controlled by thedevices A to D.

According to the first to fifth embodiments, as described above, thebuffers that can store transfer data are provided in association withthe respective devices. Thus, the time needed for handshake at the timeof data transfer can be reduced, and the data transfer speed can beincreased. In addition, since the occupation time of the bus can bereduced, the data transfer efficiency can be enhanced. Moreover, sinceeach device includes the memory that can store a plurality of requestinstructions and each buffer includes a plurality of entries, the datatransfer can be executed out of order, and the data transfer efficiencycan be improved.

FIG. 30 is a block diagram of a host processor 70 and an MC 10 that areincluded in an LSI 1 according to a modification of the first to fifthembodiments. As is shown in FIG. 30, the host processor 70 sends to theMC 10 not the data transfer request instruction itself, but a task ortask-related information. The MC 10 includes a scheduler 13, whichanalyzes the task that is sent from the host processor 70, andrecognizes data transfer that is necessary for execution of the task.Based on the analysis result, the scheduler 13 generates requestinstructions and registers them in the request table 12. If an order ofpriority is needed for the data transfer, the scheduler 13 registers theinformation of the order of priority in the request table 12 as apriority table. In this case, the arbiter 11 refers to the prioritytable and executes data transfer in the order of request instructionsbeginning with one having a highest priority. In this manner, theabove-described embodiments can be applied to the case in which therequest instructions are generated within the MC 10.

In the above-described embodiments, data transfer is controlled by theMC 10, which is provided separately from the devices A to D. Howeverthere is no need to provide the MC 10 for the purpose of data transfer.Any one of the devices may double as the MC 10. For example, as shown inFIG. 31, in an LSI 1 including devices A to E, the device E may alsoserve as the MC 10. Depending on cases, the device that serves as the MC10 may be changed. Besides, as shown in FIG. 32, an eDRAM (embeddedDRAM) may be used for the SDBs and DDBs. Each device may include theassociated SDB and DDB as integral parts. Further, in theabove-described embodiments, all devices included in the LSI have SDBsand DDBs. However, even in a case where only some of the devices areprovided SDBs and DDBs, the same advantageous effects can be obtained.There may be a case in which the device has only one of the SDB and DDB.

In the case where the request instruction is output from the MC 10 afterthe transfer-source device writes data in the SDB, as in the firstembodiment, the request table 12 may not have information relating tothe SDB. It should suffice if the request table 12 has informationrelating to the DDB. The reason is that the SDB must be in use at thetime instant when the request instruction has been output.

In the second to fifth embodiments, too, the request instruction may beoutput from not only the host processor 70 but also the devices A to D.Needless to say, the third and fourth embodiments are applicable to thecase in which the MC 10 checks the empty/non-empty state of the SDB, asin the second embodiment.

The data transfer device and semiconductor integrated circuit device,which have been described in connection with the above embodiments, areapplicable to an image processor, for instance. FIG. 33 is a blockdiagram that shows an image rendering processor system LSI 2 includingthe data transfer device according to the above-described embodiments.

As is shown in FIG. 33, the image rendering processor system LSI 2according to the embodiments includes a host processor 3, an I/Oprocessor 4, a main memory 5 and a graphic processor 6. The hostprocessor 3 and graphic processor 6 are connected over a processor busBUS so as to be mutually communicable.

The host processor 3 includes a main processor 80, I/O sections 81 to83, and a plurality of digital signal processors (DSPs) 84. Thesecircuit blocks are connected over a local network LN1 so as to bemutually communicable. The main processor 80 controls the operations ofthe respective circuit blocks in the host processor 3. The I/O section81 executes data transmission/reception via the I/O processor 4 betweenthe host processor 3 and the outside. The I/O section 82 executes datatransmission/reception with the main memory 5. The I/O section 83executes data transmission/reception with the graphic processor 6 viathe processor bus BUS. The digital signal processors 84 execute signalprocessing on the basis of data that is read out of the main memory 5 orfrom the outside.

The I/O processor 4 connects the host processor 3 to, for instance, ageneral-purpose bus, a peripheral such as an HDD or a DVD (DigitalVersatile Disc) drive, and a network. In this case, the HDD or DVD drivemay be mounted on the LSI 2 or may be provided outside the LSI 2.

The main memory 5 stores programs that are necessary for the operationof the host processor 3. The programs are read out, for example, from anHDD (not shown) and are loaded in the main memory 5.

The graphic processor 6 includes an MC 90, I/O sections 91 and 92, andan arithmetic process section 93. The MC 90 is the MC 10 that has beendescribed in connection with the first to fifth embodiments. The I/Osection 91 controls input/output from/to the host processor 3 via theprocessor bus BUS. The I/O section 92 controls, for example,input/output from/to various general-purpose buses such as a PCI bus,audio/video input/output, and input/output from/to an external memory.The arithmetic process section 93 executes image processing arithmeticoperations.

The arithmetic process section 93 includes a rasterizer 94, a pluralityof pixel shaders 95-0 to 95-3, and a packet management unit 96. In thisembodiment, the number of pixel shaders is four. However, the number ofpixel shaders is not limited to four, and may be 8, 16, 32, etc.

The rasterizer 94 generates pixels in accordance with input graphicinformation. The pixel is a minimum-unit region that is handled when agiven graphic is to be rendered. A graphic is rendered by a set ofpixels. The generated pixels are input to the pixel shaders 95-0 to95-3. The pixel shaders 95-0 to 95-3 execute arithmetic operations basedon pixels that are input from the rasterizer 94, and generate image dataon realize memories. The packet management unit 96 includes realizememories that are provided in association with the pixel shaders 95-0 to95-3, respectively. The realize memories are, for instance, eDRAMs thatare formed on the same semiconductor substrate. The realize memoriesstore pixel data that are rendered by the pixel shaders 95-0 to 95-3.The MC 90, I/O sections 91 and 92, rasterizer 94 and packet managementunit 96 are connected over a local network LN2 so as to be mutuallycommunicable.

In the above structure, the pixel data that are stored in the realizememories are transferred to a FIFO that is included in the I/O section92, and are output to the outside. The MC 90 controls data transferbetween the realize memories and the FIFO of the I/O section 92 by themethod that has been described in connection with the first to fifthembodiments. Specifically, the MC 90 corresponds to the MC 10 in theabove-described embodiments. Since the image rendering apparatus handlesan enormous amount of data, the method of the above-describedembodiments is very effective. The MC 10 may be provided within thearithmetic process section 93. In this case, the MC 10 controls datatransfer between the rasterizer 94 and pixel shaders 95-0 to 95-3 anddata transfer between the pixel shaders 95-0 to 95-3 and the realizememories.

Additional advantages and modifications will readily occur to thoseskilled in the art. Therefore, the invention in its broader aspects isnot limited to the specific details and representative embodiments shownand described herein. Accordingly, various modifications may be madewithout departing from the spirit or scope of the general inventiveconcept as defined by the appended claims and their equivalents.

1. A semiconductor integrated circuit device which includes a firstsemiconductor device and a second semiconductor device and executes datatransmission/reception between the first and second semiconductordevices, comprising: first and second buffer circuits which store data;a data bus which transmits the data between the first and second buffercircuits; the first semiconductor device which reads out the transferdata into the first buffer circuit in a case where the first buffercircuit includes an empty area at a time of transferring the data; acontrol circuit which transfers the transfer data, which is stored inthe first buffer circuit, to the second buffer circuit via the data busin a case where the second buffer circuit includes an empty area at thetime of transferring the data, the control circuit acquiring a right ofuse of the data bus after the first semiconductor device writes thetransfer data into the first buffer circuit, and disclaiming the rightof use of the data bus after the transfer data is transferred to thesecond buffer circuit; and the second semiconductor device which readsout the transfer data transferred to the second buffer circuit.
 2. Asemiconductor integrated circuit device which includes a plurality ofsemiconductor devices, comprising: a first buffer circuit provided inassociation with each of the plurality of semiconductor devices,transfer data being read out from the associated semiconductor deviceinto the first buffer circuit when the associated semiconductor devicefunctions as a transfer-source semiconductor device; a second buffercircuit provided in association with each of the plurality ofsemiconductor devices, the transfer data being transferred and writtenin the second buffer circuit when the associated semiconductor devicefunctions as a transfer-destination semiconductor device; a data buswhich transmits the transfer data between the semiconductor devices; anda control circuit which acquires a right of use of the data bus when thetransfer data is read out into the first buffer circuit, transfers thetransfer data via the data bus to the second buffer circuit associatedwith the semiconductor device functioning as the transfer-destinationsemiconductor device, and disclaims the right of use of the data busafter the transfer of the transfer data is completed.
 3. The deviceaccording to claim 2, wherein at the time of the data transfer, thecontrol circuit outputs a read-out request instruction, which requestsread-out of the transfer data to the first buffer circuit, to thesemiconductor device functioning as the transfer-source semiconductordevice, the semiconductor device functioning as the transfer-sourcesemiconductor device reads out the transfer data to the first buffercircuit in response to the read-out request instruction, and returns anacknowledge signal to the control circuit after completion of theread-out, and the control circuit acquires the right of use of the databus in response to the acknowledge signal.
 4. The device according toclaim 3, wherein in a case where the first buffer circuit associatedwith the semiconductor device functioning as the transfer-sourcesemiconductor device includes an empty area, the control circuit outputsthe read-out request instruction to the semiconductor device.
 5. Thedevice according to claim 3, wherein in a case where the second buffercircuit associated with the semiconductor device functioning as thetransfer-destination semiconductor device includes an empty area, thecontrol circuit transfers the transfer data to the second buffercircuit.
 6. The device according to claim 2, wherein at the time of thedata transfer, the control circuit outputs a plurality of read-outrequest instructions, each of which request read-out of the transferdata to the first buffer circuit, to the semiconductor devicefunctioning as the transfer-source semiconductor device, thesemiconductor device functioning as the transfer-source semiconductordevice reads out the transfer data to the first buffer circuit inresponse to the read-out request instruction, and returns an acknowledgesignal to the control circuit after completion of the read-out, thecontrol circuit acquires the right of use of the data bus in response tothe acknowledge signal, the semiconductor device functioning as thetransfer-source semiconductor device stores a plurality of the read-outrequest instructions, and the semiconductor device functioning as thetransfer-source semiconductor device reads out the transfer data intothe first buffer circuit in an order different from an order in whichthe read-out request instructions are received.
 7. The device accordingto claim 2, wherein the first buffer circuit includes a plurality ofentries which stores the transfer data, and the control circuittransfers the transfer data to the second buffer circuit in an orderdifferent from an order in which the transfer data are stored in thefirst buffer circuit.
 8. The device according to claim 7, wherein thecontrol circuit preferentially transfers the transfer data, for which anempty area is available in the second buffer associated with thesemiconductor device functioning as the transfer-destination device, tothe second buffer circuit.
 9. The device according to claim 2, whereinthe semiconductor device functioning as the transfer-sourcesemiconductor device outputs to the control circuit a transfer requestinstruction for transfer of the transfer data to the semiconductordevice functioning as the transfer-destination semiconductor device whenthe semiconductor device functioning as the transfer-sourcesemiconductor device writes the transfer data in the first buffercircuit, and the control circuit transfers the transfer data to thesemiconductor device functioning as the transfer-destinationsemiconductor device in accordance with the transfer requestinstruction.
 10. The device according to claim 9, wherein the controlcircuit transfers the transfer data, for which an empty area isavailable in the second buffer associated with the semiconductor devicefunctioning as the transfer-destination device, to the second buffercircuit.
 11. The device according to claim 2, wherein the semiconductordevice functioning as the transfer-destination device reads out thetransfer data after the transfer data is written in the associatedsecond buffer circuit.
 12. The device according to claim 11, wherein thesecond buffer circuit includes a plurality of entries which stores thetransfer data, and the semiconductor device functioning as thetransfer-destination semiconductor device reads out the transfer data inan order different from an order in which the transfer data are storedin the second buffer circuit.
 13. The device according to claim 2,wherein the control circuit includes: a request table which storesinformation relating to an empty/non-empty state of the first buffercircuit of the semiconductor device functioning as the transfer-sourcesemiconductor device, and information relating to an empty/non-emptystate of the second buffer circuit of the semiconductor devicefunctioning as the transfer-destination semiconductor device; and anarbiter which determines between which of the semiconductor devices thedata transfer is to be executed, in accordance with the information inthe request table.
 14. The device according to claim 2, wherein the databus has an interconnection-type network architecture which includestransmission lines associated with all combinations of the semiconductordevices.
 15. The device according to claim 2, wherein the first andsecond buffer circuits are made of an embedded DRAM.
 16. A data transfermethod for data transfer between a first semiconductor device and asecond semiconductor device, which are connected over a data bus,comprising: causing the first semiconductor device, which functions as atransfer-source semiconductor device, to read out transfer data into afirst buffer circuit; causing a control circuit to confirm completion ofthe read-out of the transfer data into the first buffer circuit, and toacquire a right of use of the data bus; causing the control circuit totransfer the transfer data, which is stored in the first buffer circuit,to a second buffer circuit via the data bus; causing the control circuitto disclaim the right of use of the data bus after the transfer of thetransfer data; causing the second semiconductor device to read out thetransfer data transferred to the second buffer circuit.
 17. The methodaccording to claim 16, wherein while the control circuit acquires aright of use of the data bus and transfers the transfer data to thesecond buffer circuit, the first semiconductor device functioning as thetransfer-source semiconductor device reads out the transfer data, whichis to be transferred next, into the first buffer circuit.
 18. The methodaccording to claim 17, wherein while the second semiconductor devicereads out the transfer data, the control circuit acquires the right ofuse of the data bus in connection with the transfer data which is to betransferred next, and transfer the transfer data to the second buffer.19. The method according to claim 16, further comprising: confirming anempty/non-empty state of the first buffer circuit; and confirming anempty/non-empty state of the second buffer circuit, wherein the firstsemiconductor device reads out the transfer data to the first buffercircuit in a case where an empty area is available in the first buffercircuit, and the control circuit transfers the data in the first buffercircuit to the second buffer circuit in a case where an empty area isavailable in the second buffer circuit.
 20. The method according toclaim 19, further comprising: storing information relating to theempty/non-empty state of the first buffer circuit in a request table;and storing information relating to the empty/non-empty state of thesecond buffer circuit in the request table, wherein on the basis of theinformation in the request table, the control circuit instructs thefirst semiconductor device to execute read-out of the transfer data intothe first buffer circuit, and transfers the data to the second buffercircuit from the first buffer circuit.